SystemC Simulation
SystemC Simulation
The C/C++/SystemC environment is ready to use right after installation is completed. The installer includes a supported C/C++ compiler, header files and library files required by various types of C applications (SystemC, SystemC+SCV, PLI, VHPI) C applications can be compiled with a dedicated command that sets the required defines, paths to header files, libraries to be linked, etc. This allows engineers to focus on development, rather than on the caveats of C++ compilers. A powerful set of debugging tools is also available with our solutions.
SystemC (version 2.x) is supported natively in Aldec simulators. SystemC modules are compiled to design libraries, alongside regular HDL models and the hierarchy of the simulated designs can contain any mixture of SystemC, HDL and EDIF. No interface layers need to be developed between SystemC and the HDL. Both SystemC and HDL modules are automatically connected as soon as simulation is initialized. SystemC signals history can be recorded to a simulation database and displayed in the Accelerated Waveform Viewer or the List Viewer. Other debugging tools originally developed for HDL are also available, for example the Advanced Dataflow window can display SystemC modules. An external debugger (gdb or Microsoft Visual Studio) can be connected to SystemC modules simulated in Aldec simulators, allowing designers to step through SystemC source code, set code breakpoints and more.

The SystemC Verification Library, or SCV, built on the foundation of SystemC and Testbuilder supports advanced randomization techniques, transaction recording, etc and has gained popularity among designers lately. Aldec simulators contain a complete environment for developing and simulating SCV applications. Header files and pre-compiled library files are delivered with the product and a dedicated command streamlines compilation. The development of transactors is also simplified by the Transactor Wizard.
Aldec simulators also provide generic, IEEE-standardized interfaces to VHDL and Verilog. The interfaces allow you to query and control the simulated model from custom C applications. You can scan the hierarchy of the design, monitor or force any signal in the simulator, register callback routines on events in the simulator, etc. The PLI and VHPI interfaces are commonly used in industry applications, for example you can take the third party tools that are frequently connected to Riviera-PRO via PLI or VHPI. Additionally, various C models are available for Aldec simulators from companies like Denali, Synopsys and Xilinx.
NOTE: If you are new to SCV, you can start off with the SystemC and SCV sample designs delivered with Riviera-PRO or available via the training files for that product on this site.
Aldec continues it's firm commitment to make our tools as useable for today's design engineer as is possible through constant innovation and improvement. If you are interested in what we can do to make your business more productive please do not hesitate to contact us. If you are an existing customer then feel free to provide us feedback using our support channel, as this information is used by our development team to make sure we implement the relevant technologies the industry needs.
Verification
- VHDL Simulation
- Verilog Simulation
- SystemC
- SystemVerilog
- Assertions (PSL, SVA and OVA)
- Acceleration/Emulation
- Code Coverage
- Design Rule Checker (LINT)
Specialty Solutions
- In-Hardware Simulation
- DO-254 Compliance
- MATLAB/Simulink Co-Simulation
- Verification IP
- HDL Regression Manager
- NIOS II Co-Verification
- ARM Co-Verification
- Actel RTAX Prototyping